Interrupt Driven PC System Design

Rating:
Summary: Needs a revision
Review: This is the only book I've come across that covers the 8259 and compatible PIC's in any significant detail. If you're interrested in interrupt issues on a IA32 system with 8259's then this is a decent book to read side by side with the data sheet from Intel.

Unfortunatly it has a number of flaws.

First, the book is written with the assumption that all interrupt code should be able to coexist with existing BIOS, DOS, and Windows 3.1 interrupt code. This boils down to the general assumption, which is out right stated as a fact, that only code that supports Non-Specific EOI's can be used on a "PC System", and as such a number of the 8259's modes of operation can not be used on a "PC System". All statements in bold face that include the words "PC System" should be questioned.

Second, it is somewhat repetative between chapters, and between descriptions of the 8259's modes of operation.

Third, it does not cover a number of associated topics on interrupt service handling. This steems mainly from the assumption that a "PC System" only runs BIOS, DOS, or Windows 3.1 interrupt code. These topics include the 8259's register access latencies, IO port access and memory synchronization and latency issues on IA32, livelock, and delayed interrupt handling such as in critical sections to name a few.

Lastly, it needs a major update. It mentions "string transfers", basicly a rep ins or rep movs instruction sequence, as a "more sophisitcated transfer technique." More likely the section should be updated to include the MMX and SSE instruction sets.

Modern systems include APIC's, both Local APIC's and IOAPIC's. These systems further complicate the PC interrupt subsystem because multiple buses may have seperate interrupt controllers thus bluring the destinction between what interrupts can be set as edge triggered, and what interrupts can be set as level triggered. This also changes the effects of the ELCR's.

A number of these systems actually report a number of devices that support level trigger mode as edge trigger mode. This changes the notion from "is this device edge or level triggered" to "can I query the device for interrupt request status".


Over all, this book does a decent job putting a software oriented perspective on the 8259 which you won't get from reading the Intel data sheet alone. Its unfortunate that certain assumptions are stated as fact thus dating the material covered.