A Verilog Hdl Primer

Rating:
Summary: Not a very good book
Review: Occasionally you see books that seem to be compiled by the author's lecture notes, this is one of them. It would still be ok if the notes were good, however this one isn't. It does it's job presenting the basics of Verilog, but on harder to understand concepts such as blocking/non-blocking procedural assignments and procedural continuous assignment, the author does an aweful job explaining it, which is where it counts the most. Similar problems appear throughout the book, and I can never understand why it has attained a four star rating, which is when I purchased it. If you can find a better book, go for it!

Rating:
Summary: Concise & complete
Review: That's the way to describe it. The matter is not very verbose. It is comp[avt & the book moves fast. This is achieved, unfortunately, at the expense of a sufficient number of complete, working examples, which makes this book slightly unsiited for the semi-competent but the competent will be pleased with the fast pace at which concepts are introduced.

Rating:
Summary: Regurgitation of LRM
Review: This book is basically a regurgitation of the language reference manual and really does not give the reader any insight into when and how to use particular language constructs. For example on page 148 the author discusses module ports and has an example of a port redeclaration, but he neglects to discuss why you would wish to redeclare a port as a wire. If you are learning Verilog because you are going to use it in an actual design look elsewhere.

Rating:
Summary: Regurgitation of LRM
Review: This book is well organized.All the chapters are thoroughly written and hence easily understood by a beginner.I would personally refer this book both for a beginner and a practicing engineer.

Rating:
Summary: Well Organised
Review: This book is well organized.All the chapters are thoroughly written and hence easily understood by a beginner.I would personally refer this book both for a beginner and a practicing engineer.

Rating:
Summary: A must have book
Review: While some might say that it's a beginners' book, you will
end up using this book the most. I have several Verilog
books in my cube at my work, but this is the book my
colleagues come very often to look up. This has excellent
and authentic descriptions of all Verilog language rules
and primitives. It also explains how and when to use
different Verilog constructs. I bet you will not regret
having this book.